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FEATURES
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LTC2273/LTC2272 16-Bit, 80Msps/65Msps Serial Output ADC DESCRIPTION
The LTC(R)2273/LTC2272 are 80Msps/65Msps, 16-bit A/D converters with a high speed serial interface. They are designed for digitizing high frequency, wide dynamic range signals with an input bandwidth of 700MHz. The input range of the ADC can be optimized using the PGA front end. The output data is serialized according to the JEDEC serial interface for data converters specification (JESD204). The LTC2273/LTC2272 are perfect for demanding applications where it is desirable to isolate the sensitive analog circuits from the noisy digital logic. The AC performance includes a 77.7dB Noise Floor and 100dB spurious free dynamic range (SFDR). Ultra low internal jitter of 80fs RMS allows undersampling of high input frequencies with excellent noise performance. Maximum DC specs include 4.5LSB INL and 1LSB DNL (no missing codes) over temperature. The encode clock inputs, ENC+ and ENC-, may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. A clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
n
High Speed Serial Interface (JESD204) Sample Rate: 80Msps/65Msps 77.7dBFS Noise Floor 100dB SFDR SFDR >90dB at 140MHz (1.5VP-P Input Range) PGA Front End (2.25VP-P or 1.5VP-P Input Range) 700MHz Full Power Bandwidth S/H Optional Internal Dither Single 3.3V Supply Power Dissipation: 1100mW/990mW Clock Duty Cycle Stabilizer Pin Compatible Family 105Msps: LTC2274 80Msps: LTC2273 65Msps: LTC2272 40-Pin 6mm x 6mm QFN Package
APPLICATIONS
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Telecommunications Receivers Cellular Base Stations Spectrum Analysis Imaging Systems ATE
TYPICAL APPLICATION
3.3V SENSE VCM 1.25V COMMON MODE BIAS VOLTAGE INTERNAL ADC REFERENCE GENERATOR FAM SYNC+ 8B/10B ENCODER 16 20 SYNC- OVDD 1.2V TO 3.3V 0.1F 50 AIN + ANALOG INPUT AIN - CMLOUT+ 50 AMPLITUDE (dBFS) ASIC OR FPGA
128k Point FFT, fIN = 4.93MHz, -1dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
2.2F
+
SERIAL RECEIVER
+
S/H AMP
-
CLOCK CLOCK/DUTY CYCLE CONTROL ENC+ ENC-
16-BIT PIPELINED ADC CORE
SERIALIZER CORRECTION LOGIC CMLOUT-
-
SCRAMBLER/ PATTERN GENERATOR PGA DITH MSBINV SHDN
20X PLL GND
VDD
3.3V
0.1F
0.1F
22732 TA01
0
10
20 30 FREQUENCY (MHz)
40
22732 G04
PAT1 PAT0 SCRAM SRR1 SRR0
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LTC2273/LTC2272 ABSOLUTE MAXIMUM RATINGS
OVDD = VDD (Notes 1, 2)
PIN CONFIGURATION
TOP VIEW MSBINV SCRAM SENSE PAT1 PAT0 SHDN GND GND FAM 30 GND 29 SYNC- 28 SYNC+ 27 GND 41 26 GND 25 OVDD 24 CMLOUT+ 23 CMLOUT- 22 OVDD 21 GND 11 12 13 14 15 16 17 18 19 20 VDD GND VDD GND SRR0 SRR1 ISMODE SHDN DITH PGA VCM 40 39 38 37 36 35 34 33 32 31 VDD 1 VDD 2 GND 3 AIN+ 4 AIN- 5 GND 6 GND 7 GND 8 ENC+ 9 ENC- 10
Supply Voltage (VDD) ................................... -0.3V to 4V Analog Input Voltage (Note 3) .......-0.3V to (VDD + 0.3V) Digital Input Voltage......................-0.3V to (VDD + 0.3V) Digital Output Voltage ................ -0.3V to (OVDD + 0.3V) Power Dissipation .............................................2000mW Operating Temperature Range LTC2273C/LTC2272C ............................... 0C to 70C LTC2273I/LTC2272I.............................. -40C to 85C Storage Temperature Range................... -65C to 150C Digital Output Supply Voltage (OVDD) .......... -0.3V to 4V
UJ PACKAGE 40-LEAD (6mm 6mm) PLASTIC QFN
TJMAX = 150C, JA = 22C/W EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC2273CUJ#PBF LTC2273IUJ#PBF LTC2272CUJ#PBF LTC2272IUJ#PBF LEAD BASED FINISH LTC2273CUJ LTC2273IUJ LTC2272CUJ LTC2272IUJ TAPE AND REEL LTC2273CUJ#TRPBF LTC2273IUJ#TRPBF LTC2272CUJ#TRPBF LTC2272IUJ#TRPBF TAPE AND REEL LTC2273CUJ#TR LTC2273IUJ#TR LTC2272CUJ#TR LTC2272IUJ#TR PART MARKING* LTC2273UJ LTC2273UJ LTC2272UJ LTC2272UJ PART MARKING* LTC2273UJ LTC2273UJ LTC2272UJ LTC2272UJ PACKAGE DESCRIPTION 40-Lead (6mm x 6mm) Plastic QFN 40-Lead (6mm x 6mm) Plastic QFN 40-Lead (6mm x 6mm) Plastic QFN 40-Lead (6mm x 6mm) Plastic QFN PACKAGE DESCRIPTION 40-Lead (6mm x 6mm) Plastic QFN 40-Lead (6mm x 6mm) Plastic QFN 40-Lead (6mm x 6mm) Plastic QFN 40-Lead (6mm x 6mm) Plastic QFN TEMPERATURE RANGE 0C to 70C -40C to 85C 0C to 70C -40C to 85C TEMPERATURE RANGE 0C to 70C -40C to 85C 0C to 70C -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS Differential Analog Input (Note 5) TA = 25C Differential Analog Input (Note 5) Differential Analog Input (Note 6) External Reference Internal Reference External Reference SYMBOL Integral Linearity Error Integral Linearity Error Differential Linearity Error Offset Error Offset Drift Gain Error Full-Scale Drift Transition Noise MIN
l l l l
TYP 1.2 1.5 0.3 1 10 0.2 30 15 3
MAX 4 4.5 1 8.5 1.5
UNITS LSB LSB LSB mV V/C %FS ppm/C ppm/C LSBRMS
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LTC2273/LTC2272 ANALOG INPUT
SYMBOL VIN VIN, CM IIN ISENSE CIN tAP tJITTER CMRR BW-3dB
The l denotes denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
PARAMETER Analog Input Range (AIN+ - AIN-) Analog Input Common Mode Analog Input Leakage Current SENSE Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio Full Power Bandwidth 1V < (AIN+ = AIN-) <1.5V RS 25 CONDITIONS 3.135V VDD 3.465V Differential Input (Note 7) 0V AIN+, AIN- VDD (Note 10) 0V SENSE VDD (Note 11) Sample Mode ENC+ < ENC- Hold Mode ENC+ > ENC-
l l l
MIN 1 -1 -3
TYP 1.5 or 2.25 1.25
MAX 1.5 1 3
UNITS VP-P V A A pF pF ns fsRMS dB MHz
6.7 1.8 1 80 80 700
DYNAMIC ACCURACY
SYMBOL PARAMETER SNR Signal-to-Noise Ratio
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 4)
LTC2273 CONDITIONS 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 15MHz Input (2.25V Range, PGA = 0), TA = 25C 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1), TA = 25C 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1) SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 15MHz Input (2.25V Range, PGA = 0), TA = 25C 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1), TA = 25C 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1)
l l
LTC2272 MAX MIN TYP 77.6 75.4 76.5 76.2 77.5 77.2 75.3 77.2 75.1 74.8 76.3 74.5 75.9 74.3 100 100 85 84 95 95 100 86 94 92 85 90 80 85 MAX UNITS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
MIN
TYP 77.6 75.4
76.5 76.2
77.5 77.2 75.3 77.2 75.1 74.8 76.3 74.5 75.9 74.3 100 100
l
74.5 74.2
74.5 74.2
85 84
95 95 100 86 94 92 85 90 80 85
l
84 83
84 83
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LTC2273/LTC2272 DYNAMIC ACCURACY
SYMBOL PARAMETER SFDR Spurious Free Dynamic Range 4th Harmonic or Higher
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS unless otherwise noted. (Note 4)
LTC2273 CONDITIONS 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1)
l
LTC2272 MAX MIN TYP 100 100 90 100 100 100 100 95 100 90 95 77.5 75.3 76.3 75.9 77.4 77 75.2 76.7 75 74.7 75.3 74.3 73.4 73.4 105 105 105 105 105 105 100 100 100 100 115 115 97 115 115 115 115 110 110 105 105 MAX UNITS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS
MIN
TYP 100 100
90
100 100 100 100 95 100 90 95 77.5 75.3
l
90
90
S/(N+D) Signal-to-Noise Plus Distortion Ratio
5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 15MHz Input (2.25V Range, PGA = 0), TA = 25C 15MHz Input (2.25V Range, PGA = 0 15MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1), TA = 25C 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1)
l
76.3 75.9
77.4 77 75.2 76.7 75 74.7 75.3 74.3 73.4 73.4 105 105 105 105 105 105 100 100 100 100 115 115
l
74.4 74.1
74.4 74.1
SFDR
Spurious Free Dynamic Range at -25dBFS Dither "OFF"
5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1)
SFDR
Spurious Free Dynamic Range at -25dBFS Dither "ON"
5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1)
l
97
115 115 115 115 110 110 105 105
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LTC2273/LTC2272
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance CONDITIONS IOUT = 0 IOUT = 0 3.135V VDD 3.465V -1mA | IOUT | 1mA
l l l
COMMON MODE BIAS CHARACTERISTICS
MIN 1.15
TYP 1.25 40 1 2
MAX 1.35
UNITS V
ppm/C
mV/V
DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL VID VICM RIN CIN VSID VSICM RSIN CSIN VIH VIL IIN CIN VOH PARAMETER Differential Input Voltage Common Mode Input Voltage Input Resistance Input Capacitance SYNC Differential Input Voltage SYNC Common Mode Input Voltage SYNC Input Resistance SYNC Input Capacitance High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance Output High Level Directly-Coupled 50 to OVDD Directly-Coupled 100 Differential AC-Coupled Directly-Coupled 50 to OVDD Directly-Coupled 100 Differential AC-Coupled Directly-Coupled 50 to OVDD Directly-Coupled 100 Differential AC-Coupled Single-Ended Differential VDD = 3.3V VDD = 3.3V VIN = 0V to VDD (Note 7) Internally Set Externally Set (Note 7) CONDITIONS (Note 7) Internally Set Externally Set (Note 7) (See Figure 2) Encode Inputs (ENC+, ENC-)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
MIN
l
TYP
MAX
UNITS V
0.2 1.6 1.4 6 3 3.0
V k pF V
SYNC Inputs (SYNC+, SYNC-)
l
0.2 1.6 1.1 16.5 3 2.2
V k pF V 0.8 10 V A pF V V V V V V V V V 65
Logic Inputs (DITH, PGA, MSBINV, SCRAM, FAM, SHDN, SRR1, SRR0, ISMODE, PAT1, PAT0)
l l l
2
1.5 OVDD OVDD - 0.2 OVDD - 0.2 OVDD - 0.4 OVDD - 0.6 OVDD - 0.6 OVDD - 0.2 OVDD - 0.4 OVDD - 0.4
l
High-Speed Serial Outputs (CMLOUT+, CMLOUT-)
VOL
Output Low Level
VOCM
Output Common Mode Voltage Output Resistance
ROUT
35
50 100
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LTC2273/LTC2272
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 4)
LTC2273 SYMBOL PARAMETER VDD PSHDN OVDD Analog Supply Voltage Shutdown Power Output Supply Voltage SHDN = VDD CMLOUT Directly-Coupled, 50 to OVDD (Note 7) CMLOUT Directly-Coupled, 100 Diff. (Note 7) CMLOUT AC-Coupled (Note 7) DC Input CMLOUT Directly-Coupled, 50 to OVDD CMLOUT Directly-Coupled, 100 Diff. CMLOUT AC-Coupled DC Input
l
POWER REQUIREMENTS
LTC2272 MAX MIN TYP 3.3 5 VDD VDD VDD 1.2 1.4 1.4 300 8 16 16 1221 990 1122 VDD VDD VDD 340 MAX 3.465 UNITS V mW V V V mA mA mA mA mW 3.465 3.135
CONDITIONS
MIN
l 3.135
TYP 3.3 5
1.2 1.4 1.4 233 8 16 16 1100
IVDD IOVDD
Analog Supply Current Output Supply Current
l l
370
PDIS
Power Dissipation
l
TIMING CHARACTERISTICS
SYMBOL PARAMETER fS tCONV tL tH tAP tBIT, UI tJIT tR, tF tSU tHD tCS LATP LATSC LATSD Sampling Frequency Conversion Period ENC Clock Low Time ENC Clock High Time Sample-and-Hold Aperture Delay Period of a Serial Bit Total Jitter of CMLOUT (P-P) Differential Rise and Fall Time of CMLOUT (20% to 80%) SYNC to ENC Clock Setup Time ENC Clock to SYNC Hold Time ENC Clock to SYNC Delay Pipeline Latency Latency from SYNC Active to COMMA Out Latency from SYNC Release to DATA Out
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
LTC2273 CONDITIONS (Note 9) (Note 7) (Note 7)
l l l
LTC2272 MAX 80 MIN 20 1/fS 25 25 5.03 5.03 7.69 7.69 0.7 tCONV/20 0.35 0.35 50 2 2.5 tCONV - tSU tHD 9 3 2 tCONV - tSU 110 25 25 TYP MAX 65 UNITS MHz s ns ns ns s UI ps ns ns ns Cycles Cycles Cycles
MIN 20
TYP 1/fS
4.06 4.06
6.25 6.25 0.7 tCONV/20
BER = 1E-12 (Note 7)
l
RTERM = 50, CL = 2pF l (Note 7) (Note 7) (Note 7) (Note 7)
l l l
50 2 2.5 tHD
110
9 3 2
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3.3V, fSAMPLE = 105MHz differential ENC+/ENC- = 2VP-P sine wave with 1.6V common mode, input range = 2.25VP-P with differential drive (PGA = 0), unless otherwise specified. Note 5: Integral nonlinearity is defined as the deviation of a code from a "best fit straight line" to the transfer curve. The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from -1/2LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2's complement output mode. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3.3V, fSAMPLE = 80Msps (LTC2273) or 65Msps (LTC2272) input range = 2.25VP-P with differential drive. Note 9: Recommended operating conditions. Note 10: The dynamic current of the switched capacitors analog inputs can be large compared to the leakage current and will vary with the sample rate. Note 11: Leakage current will have higher transient current at power up. Keep drive resistance at or below 1k.
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LTC2273/LTC2272 TIMING DIAGRAMS
tAP ANALOG INPUT N tCONV ENC+ N+1 N+2 N+8 N+9 N + 10
tH tL
INTERNAL PARALLEL DATA INTERNAL 8B/10B DATA
N-6
N-5
N-4
N+3
N+4
N-9 tBIT
N-8
N-7 LATP
N
N+1
CMLOUT+/CMLOUT- N - 10 N-9 N-8 N-1 N
22732 TD01
Analog Input to Serial Data Out Timing
tCONV N N+1 tHD ENC+ tCS(MIN) SYNC+ tCS(MAX) CMLOUT+/CMLOUT- N - 10 N-9 N-8 N-7 K28.5 (x2) K28.5 (x2)
22732 TD02
N+3 N+2 N+4 N+5
ANALOG INPUT
N-1
tSU
LATSC
SYNC+ Falling Edge to Comma (K28.5) Timing
tCONV N N+1 tHD ENC+ tCS(MIN) SYNC+ tCS(MAX) CMLOUT+/CMLOUT- K28.5 (x2) K28.5 (x2) K28.5 (x2) N-7 N-6
22732 TD03
N+3 N+2 N+4
ANALOG INPUT
N-1
tSU
LATSD
SYNC+ Rising Edge to Data Timing
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LTC2273/LTC2272 TYPICAL PERFORMANCE CHARACTERISTICS
unless otherwise noted. LTC2273: Integral Non-Linearity (INL) vs Output Code
2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0
VDD = 3.3V, OVDD = 1.5V, TA = 25C, FS = 80Msps,
LTC2273: Differential NonLinearity (DNL) vs Output Code
1.0 0.8 0.6 DNL ERROR (LSB) 0.4 10000 9000 8000 7000
LTC2273: AC Grounded Input Histogram
INL ERROR (LSB)
0.0 -0.2 -0.4 -0.6 -0.8
COUNT
0 16384 32768 49152 OUTPUT CODE 65536
22732 G02
0.2
6000 5000 4000 3000 2000 1000 0 32769 32779 32789 OUTPUT CODE 32799
22732 G03
0
16384
32768 49152 OUTPUT CODE
65536
22732 G01
-1.0
LTC2273: 128k Point FFT, fIN = 5.1MHz, -1dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2273: 64k Point FFT, fIN = 14.8MHz, -1dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2273: 64k Point FFT, fIN = 14.8MHz, -10dBFS, PGA = 0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
10
20 30 FREQUENCY (MHz)
40
22732 G04
0
10
20 30 FREQUENCY (MHz)
40
22732 G05
AMPLITUDE (dBFS)
0
10
20 30 FREQUENCY (MHz)
40
22732 G06
LTC2273: SFDR vs Input Level, fIN = 15MHz, PGA = 0, Dither "Off"
140 130 120 140 130 120
LTC2273: SFDR vs Input Level, fIN = 15MHz, PGA = 0, Dither "On"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2273: 64k Point 2-Tone FFT, fIN = 14.01MHz and 15.81MHz, -7dBFS, PGA = 0
SFDR (dBc AND dBFS)
SFDR (dBc AND dBFS)
100 90 80 70 60 50 40 30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
100 90 80 70 60 50 40
0
30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
AMPLITUDE (dBFS)
110
110
0
0
10
20 30 FREQUENCY (MHz)
40
22732 G09
22732 G07
22732 G08
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LTC2273/LTC2272 TYPICAL PERFORMANCE CHARACTERISTICS
unless otherwise noted. LTC2273: 64k Point 2-Tone FFT, fIN = 14.01MHz and 15.8MHz, -15dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
VDD = 3.3V, OVDD = 1.5V, TA = 25C, FS = 80Msps,
LTC2273: 64k Point FFT, fIN = 70MHz, -1dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2273: 64k Point FFT, fIN = 70MHz, -1dBFS, PGA = 1
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
10
20 30 FREQUENCY (MHz)
40
22732 G10
0
10
20 30 FREQUENCY (MHz)
40
22732 G11
AMPLITUDE (dBFS)
0
10
20 30 FREQUENCY (MHz)
40
22732 G12
LTC2273: 128k Point FFT, fIN = 70MHz, -20dBFS, PGA = 0, Dither "Off"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2273: 128k Point FFT, fIN = 70MHz, -20dBFS, PGA = 0, Dither "On"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2273: 64k Point FFT, fIN = 140.2MHz, -1dBFS, PGA = 1
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
10
20 30 FREQUENCY (MHz)
40
22732 G13
0
10
20 30 FREQUENCY (MHz)
40
22732 G14
AMPLITUDE (dBFS)
0
10
20 30 FREQUENCY (MHz)
40
22732 G15
LTC2273: SFDR vs Input Level, fIN = 140MHz, PGA = 1, Dither "Off"
140 130 120 140 130 120
LTC2273: SFDR vs Input Level, fIN = 140MHz, PGA = 1, Dither "On"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2273: 64k Point FFT, fIN = 170.2MHz, -1dBFS, PGA = 1
SFDR (dBc AND dBFS)
SFDR (dBc AND dBFS)
100 90 80 70 60 50 40 30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
100 90 80 70 60 50 40
0
30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
AMPLITUDE (dBFS)
110
110
0
0
10
20 30 FREQUENCY (MHz)
40
22732 G18
22732 G16
22732 G17
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LTC2273/LTC2272 TYPICAL PERFORMANCE CHARACTERISTICS
unless otherwise noted. LTC2273: 64k Point FFT, fIN = 250.2MHz, -1dBFS, PGA = 1
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
VDD = 3.3V, OVDD = 1.5V, TA = 25C, FS = 80Msps,
LTC2273: SFDR vs Input Frequency
105 100 95
SFDR (dBc) SNR (dBFS)
LTC2273: SNR vs Input Frequency
78
76
PGA = 0
AMPLITUDE (dBFS)
90 85 80 75 70
PGA = 0 PGA = 1
74
PGA = 1
72
0
10
20 30 FREQUENCY (MHz)
40
22732 G19
65
70
0 100 200 300 INPUT FREQUENCY (MHz) 400
22732 G20
0
100 200 300 INPUT FREQUENCY (MHz)
400
22732 G21
LTC2273: SNR and SFDR vs Sample Rate, fIN = 5.1MHz
110 105
SNR (dBFS) AND SFDR (dBC)
LTC2273: SNR and SFDR vs Supply Voltage (VDD), fIN = 5.2MHz
110 105
SNR AND SFDR (dBFS)
SFDR
SFDR
100 95 90 85 80 75 70
20 40 60 80 100 SAMPLE RATE (Msps) 120
22732 G22
100 95 90 85 80 75 70 2.8
3.0 3.2 SUPPLY VOLTAGE (V) 3.4
22732 G23
SNR
SNR
LTC2273: SFDR vs Analog Input Common Mode Voltage, 5MHz and 70MHz, -1dBFS
110 105 100 95
SFDR (dBc)
LTC2273: IVDD vs Sample Rate, 5MHz Sine, -1dBFS
400
VDD = 3.3V
5MHz
360
IVDD (mA)
VDD = 3.47V
90 85 80 75 70 65 60 0.50 0.75 1.00 1.25 1.50 1.75 2.00 ANALOG INPUT COMMON MODE VOLTAGE (V)
22732 G24
70MHz
320
VDD = 3.13V
280
240
20
45 70 95 SAMPLE RATE (Msps)
120
22732 G25
22732f
10
LTC2273/LTC2272 TYPICAL PERFORMANCE CHARACTERISTICS
unless otherwise noted. LTC2272: Integral Non-Linearity (INL) vs Output Code
2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0
DNL ERROR (LSB) 1.0 0.8 0.6
VDD = 3.3V, OVDD = 1.5V, TA = 25C, FS = 65Msps,
LTC2272: Differential NonLinearity (DNL) vs Output Code
10000 9000 8000 7000
LTC2272: AC Grounded Input Histogram
INL ERROR (LSB)
0.4
0.0 -0.2 -0.4 -0.6 -0.8 -1.0
COUNT
0 16384 32768 49152 OUTPUT CODE 65536
22732 G27
0.2
6000 5000 4000 3000 2000 1000 0 32894 32904 32914 OUTPUT CODE 32924
22732 G28
0
16384
32768 49152 OUTPUT CODE
65536
22732 G26
LTC2272: 128k Point FFT, fIN = 5.1MHz, -1dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2272: 64k Point FFT, fIN = 14.8MHz, -1dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2272: 64k Point FFT, fIN = 14.8MHz, -10dBFS, PGA = 0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
10 20 FREQUENCY (MHz)
30
22732 G29
0
10 20 FREQUENCY (MHz)
30
22732 G30
AMPLITUDE (dBFS)
0
10 20 FREQUENCY (MHz)
30
22732 G31
LTC2272: SFDR vs Input Level, fIN = 15MHz, PGA = 0, Dither "Off"
140 130 120 140 130 120
LTC2272: SFDR vs Input Level, fIN = 15MHz, PGA = 0, Dither "On"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2272: 64k Point 2-Tone FFT, fIN = 14.01MHz and 15.8MHz, -7dBFS, PGA = 0
SFDR (dBc AND dBFS)
SFDR (dBc AND dBFS)
100 90 80 70 60 50 40 30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
100 90 80 70 60 50 40
0
30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
AMPLITUDE (dBFS)
110
110
0
0
10 20 FREQUENCY (MHz)
30
22732 G34
22732 G32
22732 G33
22732f
11
LTC2273/LTC2272 TYPICAL PERFORMANCE CHARACTERISTICS
unless otherwise noted. LTC2272: 64k Point FFT, fIN = 14.01MHz and 15.8MHz, -15dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
VDD = 3.3V, OVDD = 1.5V, TA = 25C, FS = 65Msps,
LTC2272: 64k Point FFT, fIN = 70MHz, -1dBFS, PGA = 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2272: 64k Point FFT, fIN = 70MHz, -1dBFS, PGA = 1
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
10 20 FREQUENCY (MHz)
30
22732 G35
0
10 20 FREQUENCY (MHz)
30
22732 G36
AMPLITUDE (dBFS)
0
10 20 FREQUENCY (MHz)
30
22732 G37
LTC2272: 128k Point FFT, fIN = 70MHz, -20dBFS, PGA = 0, Dither "Off"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2272: 128k Point FFT, fIN = 70MHz, -20dBFS, PGA = 0, Dither "On"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2272: 64k Point FFT, fIN = 140.2MHz, -1dBFS, PGA = 1
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
10 20 FREQUENCY (MHz)
30
22732 G38
0
10 20 FREQUENCY (MHz)
30
22732 G39
AMPLITUDE (dBFS)
0
10 20 FREQUENCY (MHz)
30
22732 G40
LTC2272: SFDR vs Input Level, fIN = 140MHz, PGA = 1, Dither "Off"
140 130 120 140 130 120
LTC2272: SFDR vs Input Level, fIN = 140MHz, PGA = 1, Dither "On"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2272: 64k Point FFT, fIN = 170.2MHz, -1dBFS, PGA = 1
SFDR (dBc AND dBFS)
SFDR (dBc AND dBFS)
100 90 80 70 60 50 40 30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
100 90 80 70 60 50 40
0
30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
AMPLITUDE (dBFS)
110
110
0
0
10 20 FREQUENCY (MHz)
30
22732 G43
22732 G41
22732 G42
22732f
12
LTC2273/LTC2272 TYPICAL PERFORMANCE CHARACTERISTICS
unless otherwise noted. LTC2272: 64k Point FFT, fIN = 250.2MHz, -1dBFS, PGA = 1
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
VDD = 3.3V, OVDD = 1.5V, TA = 25C, FS = 65Msps,
LTC2272: SFDR vs Input Frequency
110 105 100 95 90 85 80 75 70
SNR (dBFS) SFDR (dBc)
LTC2272: SNR vs Input Frequency
78
76
AMPLITUDE (dBFS)
74
72
0
10 20 FREQUENCY (MHz)
30
22732 G44
65
70
0 100 200 300 INPUT FREQUENCY (MHz) 400
22732 G45
0
100 200 300 INPUT FREQUENCY (MHz)
400
22732 G46
LTC2272: SNR and SFDR vs Sample Rate, fIN = 5.2MHz
110 105
SNR (dBFS) AND SFDR (dBC)
LTC2272: SNR and SFDR vs Supply Voltage (VDD), fIN = 5.2MHz
110 105
95 90 85 80 75 70
20 40 60 80 SAMPLE RATE (Msps) 100
22732 G47
SNR AND SFDR (dBFS)
100
SFDR
100 95 90 85 80 75 70 2.8
SFDR
SNR
SNR
3.0 3.2 SUPPLY VOLTAGE (V)
3.4
22732 G48
LTC2272: SFDR vs Analog Input Common Mode Voltage, 5MHz and 70MHz, -1dBFS
110 105 100 95
SFDR (dBc)
IVDD (mA)
LTC2272: IVDD vs Sample Rate, 5MHz Sine, -1dBFS
360
5MHz
VDD = 3.3V
320
VDD = 3.47V VDD = 3.13V
90 85 80 75 70 65 60 0.50 0.75 1.00 1.25 1.50 1.75 2.00 ANALOG INPUT COMMON MODE VOLTAGE (V)
22732 G49
70MHz
280
240
20
40 60 80 SAMPLE RATE (Msps)
100
22732 G50
22732f
13
LTC2273/LTC2272 TYPICAL PERFORMANCE CHARACTERISTICS
otherwise noted. CMLOUT Dual-Dirac BER Bathtub Curve, 400Mbps
1.0E+00 1.0E-02
BIT ERROR RATE (BER)
VDD = 3.3V, OVDD = 1.5V, TA = 25C, unless
CMLOUT Dual-Dirac BER Bathtub Curve, 1.3Gbps
1.0E+00 1.0E-02
BIT ERROR RATE (BER)
1.0E-04 1.0E-06 1.0E-08
1.0E-10
1.0E-04 1.0E-06 1.0E-08
1.0E-10
1.0E-12 1.0E-14
1.0E-12 1.0E-14
0
0.2
0.4 0.6 0.8 UNIT INTERVAL (UI)
1.0
22732 G51
0
0.2
0.4 0.6 0.8 UNIT INTERVAL (UI)
1.0
22732 G52
CMLOUT Dual-Dirac BER Bathtub Curve, 1.6Gbps
1.0E+00 1.0E-02
BIT ERROR RATE (BER)
CMLOUT Eye Diagram 400Mbps
1.0E-04
100mV/DIV
1.0E-06 1.0E-08
1.0E-10 416.7ps/DIV
22732 G54
1.0E-12 1.0E-14
0
0.2
0.4 0.6 0.8 UNIT INTERVAL (UI)
1.0
22732 G53
CMLOUT Eye Diagram 1.3Gbps
CMLOUT Eye Diagram 1.6Gbps
100mV/DIV
100mV/DIV
128.2ps/DIV
22732 G55
104.2ps/DIV
22732 G56
22732f
14
LTC2273/LTC2272 PIN FUNCTIONS
VDD (Pins 1, 2, 12, 13 ): Analog 3.3V Supply. Bypass to GND with 0.1F ceramic chip capacitors. GND (Pins 3, 6, 7, 8, 11, 14, 21, 26, 27, 30, 37, 40, 41): ADC Power Ground. AIN+ (Pin 4): Positive Differential Analog Input. AIN- (Pin 5): Negative Differential Analog Input. ENC+ (Pin 9): Positive Differential Encode Input. The sampled analog input is held on the rising edge of ENC+. This pin is internally biased to 1.6V through a 6.2k resistor. Output data can be latched on the falling edge of ENC+. ENC- (Pin 10): Negative Differential Encode Input. The sampled analog input is held on the falling edge of ENC-. This pin is internally biased to 1.6V through a 6.2k resistor. Bypass to ground with a 0.1uF capacitor for a single-ended Encode signal. DITH (Pin 15): Internal Dither Enable Pin. DITH = low disables internal dither. DITH = high enables internal dither. Refer to Internal Dither section of this data sheet for details on dither operation. ISMODE (Pin 16): Idle Synchronization mode. When ISMODE is not asserted, synchronization is performed with a series of COMMAS (K28.5). When ISMODE is asserted, a special Idle SYNC mode is enabled where synchronization is performed by sending a COMMA (K28.5) followed by the appropriate data code-group (D5.6 or D16.2) for establishing a negative running disparity for the first data code-group after synchronization. SRR0 (Pin 17): Sample Rate Range Select Bit0. Used with the SRR1 pin to select the sample rate operating range. SRR1 (Pin 18): Sample Rate Range Select Bit1. Used with the SRR0 pin to select the sample rate operating range. SHDN (Pins 19, 20): Shutdown Pins. A high level on both pins will shut down the chip. A low level is required for normal operation. OVDD (Pins 22, 25): Positive Supply for the Output Drivers. Typically 1.2V to 3.3V. The minimum supply is 1.4V when applying a differential termination on the CMLOUT pins or when AC-coupling the CMLOUT pins. Bypass to ground with 0.1F ceramic chip capacitor. CMLOUT- (Pin 23): Negative High-Speed CML Output. CMLOUT+ (Pin 24): Positive High-Speed CML Output. SYNC+ (Pin 28): Sync Request Positive Input (Active Low for Compatibility with JESD204). A low level on this pin for at least two sample clock cycles will initiate frame synchronization. SYNC- (Pin 29): Sync Request Negative Input. A high level on this pin for at least two sample clock cycles will initiate frame synchronization. For single-ended operation, bypass to ground with a 0.1F capacitor and use SYNC+ as the SYNC point.
22732f
15
LTC2273/LTC2272 PIN FUNCTIONS
FAM (Pin 31): Frame Alignment Monitor Enable. A high level enables the substitution of predetermined data at the end of the frame with a K28.7 symbol for frame alignment monitoring. PAT0 (Pin 32): Pattern Select Bit0. Use with PAT1 to select a test pattern for the serial interface. PAT1 (Pin 33): Pattern Select Bit1. Use with PAT0 to select a test pattern for the serial interface. SCRAM (Pin 34): Enable Data Scrambling. A high level on this pin will apply the polynomial 1 + x14 + x15 in scrambling each ADC data sample. The scrambling takes place before the 8B/10B encoding. PGA (Pin 35): Programmable Gain Amplifier Control Pin. Low selects a front-end gain of 1, input range of 2.25VP-P . High selects a front-end gain of 1.5, input range of 1.5VP-P . MSBINV (Pin 36): Invert the MSB. A high level will invert the MSB to enable the 2's compliment format. SENSE (Pin 38): Reference Mode Select and External Reference Input. Tie SENSE to VDD to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set a full scale ADC range of 2.25V (PGA = 0). VCM (Pin 39): 1.25V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum of 2.2F Ceramic chip capacitors are recom. mended. GND (Exposed Pad) (Pin 41): ADC Power Ground. The Exposed Pad on the bottom of the package needs to be soldered to ground.
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LTC2273/LTC2272 BLOCK DIAGRAM
PIPELINED ADC STAGES AIN+ AIN- FAM SYNC+ FIFTH STAGE 8B/10B ENCODER SYNC-
+
S/H AND PGA FIRST STAGE SECOND STAGE THIRD STAGE FOURTH STAGE
-
16
DITHER SIGNAL GENERATOR CORRECTION LOGIC
20 OVDD
REFERENCE CONTROL
SERIALIZER
CMLOUT+ CMLOUT-
SENSE 0.5x VCM 1x OR 2x 2.5V REFERENCE
ADC REFERENCE
20X CLK
CLOCK DRIVER WITH DUTY CYCLE CONTROL ENC+ ENC- PGA
CONTROL LOGIC DITH MSBINV SHDN
SCRAMBLER/ PATTERN GENERATOR PAT1 PAT0 SCRAM
PLL SRR1 SRR0
VDD
GND
22732 BD
Figure 1. Functional Block Diagram
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17
LTC2273/LTC2272 DEFINITIONS
DYNAMIC PERFORMANCE TERMS Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components, except the first five harmonics. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = -20Log ((V22 + V32 + V42 + ... VN2)/V1) where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through nth harmonics. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. For example, the 3rd order IMD terms include (2fa + fb), (fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order IMD is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order IMD product. Spurious Free Dynamic Range (SFDR) The ratio of the RMS input signal amplitude to the RMS value of the peak spurious spectral component expressed in dBc. SFDR may also be calculated relative to full scale and expressed in dBFS. Full Power Bandwidth The full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when a rising ENC+ equals the ENC- voltage to the instant that the input signal is held by the sampleand-hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = -20log (2 * fIN * tJITTER) SERIAL INTERFACE TERMS 8B/10B Encoding A data encoding method designed to make an 8-bit data word (octet) more suitable for serial transmission. The resulting 10-bit word (code-group) has two fundamental strengths: 1) The receiver does not require a high-speed clock to capture the data. This is because the output code-groups are run-length limited, ensuring that there are enough transitions in the bit stream for the receiver to lock onto the data and recover the high-speed clock. 2) AC coupling is permitted because the code-groups are generated in a way that ensures the data stream is DC balanced (see Running Disparity). A table of the 256 possible input octets with the resulting 10-bit code-groups is documented in IEEE Std 802.3-2002 part3 Table 36-1. The name associated with each of the 256 data code-groups is formatted Dx.y, with x ranging from 0 to 31 and y ranging from 0 to 7. Table 36-2 of
22732f
18
LTC2273/LTC2272 DEFINITIONS
the standard defines an additional set of 12 special codegroups for non-data characters such as commas. Special code-group names begin with K instead of D. A complete 8B/10B description is found in Clause 36.2 of IEEE Std 802.3-2002 part3. Current Mode Logic (CML) A technique used to implement differential high-speed logic. CML employs differential pairs (usually n-type) to steer current into resistive loads. It is possible to implement any logic function using CML. The output swing and offset is dependant on the bias current, the load resistance, and termination resistance. This product family uses CML drivers to transmit highspeed serial data to the outside world. The output driver bias current is typically 16mA, generating a signal swing potential of 400mVP-P (800mVP-P diff.) across the combined internal and external termination resistance of 25 on each output. Code-Group The 10-bit output from an 8B/10B encoder or the 10-bit input to the 8B/10B decoder. Comma A special 8B/10B code-group containing the binary sequence "0011111" or "1100000". Commas are used for frame alignment and synchronization because a comma sequence cannot be generated by any combination of normal code-groups (unless a bit error occurs). There are three special code-groups that contain a comma, K28.1, K28.5, and K28.7. For brevity, each of these three special code-groups are often called a comma, but in the strictest sense it is the first 7 bits of these code-groups that are designated a comma. DC Balanced Signal A specially conditioned signal that may be AC coupled with minimal degradation to the signal. DC balance is achieved Frame Alignment Monitoring (FAM) After initial frame synchronization has been established, frame alignment monitoring enables the receiver to verify that code-group alignment is maintained without the loss of data. This is done by substituting a K28.7 comma for the last code-group of the frame when certain conditions are met. The receiver uses this comma as a position marker within the frame for alignment verification. After decoding the data, the receiver replaces the K28.7 comma with the original data. Idle Frame Synchronization Mode (ISMODE) A special synchronization mode where idle ordered sets are used to establish initial frame synchronization instead of K28.5 commas. An Idle Ordered Set is defined in the IEEE Std 802.3-2002 part3, Clause 36.2.4.12. In general, it is a K28.5 comma followed by either a D5.6 or a D16.2. If the running disparity after the transmission of the K28.5 comma is positive, when the average number of 1's and 0's are equal, eliminating the undesirable effects of DC wander on the receive side of the coupling capacitor. When 8B/10B coding is used, DC balance is achieved by following disparity rules (see Running Disparity). De-Scrambler A logic block that restores scrambled data to its prescrambled state. A self aligning de-scrambler is based on the same pseudo random bit sequence as the scrambler, so it requires no alignment signals. In this product family the scrambler is based on the 1 + x14 + x15 polynomial, and the self aligning process results in an initial loss of one ADC sample. Frame A group of octets or code-groups that make up one complete word. For this product family, a frame consists of two complete octets or code-groups, and constitutes one ADC sample.
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LTC2273/LTC2272 DEFINITIONS
a D16.2 will be transmitted after the comma, otherwise a D5.6 will be transmitted. The result is that the ending disparity of an idle ordered set will always be negative. Initial Frame Synchronization The process of communicating frame synchroniza-tion information to the receiver upon the request of the receiver. For JESD204 compliance, K28.5 commas are transmitted as the preamble. Once the preamble has been detected the receiver terminates the synchronization request, and the preamble transmission continues until the end of the frame. The receiver designates the first normal data word after the preamble to be the start of the data frame. Octet The 8-bit input to an 8B/10B encoder, or the 8-bit output from an 8B/10B decoder. Run-Length Limited (RLL) The result of limiting the number of consecutive 1's or 0's in a data stream by encoding the data prior to serial transmission. This process guarantees that there will be an adequate number of transitions in the serial data for the receiver to lock onto with a phase-locked loop and recover the high-speed clock. Running Disparity In order to maintain DC balance there are two possible 8B/10B output code-groups for each input octet. The running disparity is calculated to determine which of the two code-groups should be transmitted to maintain DC balance. The disparity of a code-group is analyzed in two segments called sub-blocks. Sub-block1 consists of the first six bits of a code-group and sub-block2 consists of the last four bits of a code-group. When a sub-block is more heavily weighted with 1's the running disparity is positive, and when it is more heavily weighted with 0's the running disparity is negative. When the number of 1's and 0's are equal in a sub-block, the running disparity remains unchanged. The polarity of the current running disparity determines which code-group should be transmitted to maintain DC balance. For a complete description of disparity rules, refer to IEEE Std 802.3-2002 part3, Clause 36.2.4.4. Pseudo Random Bit Sequence (PRBS) A data sequence having a random nature over a finite interval. The most commonly used PRBS test patterns may be described by a polynomial in the form of 1 + xm + xn and have a random nature for the length of up to 2n - 1 bits, where n indicates the order of the PRBS polynomial and m plays a role in maximizing the length of the random sequence. Scrambler A logic block that applies a pseudo random bit sequence to the input octets to minimize the tonal content of the high-speed serial bit stream.
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LTC2273/LTC2272 APPLICATIONS INFORMATION
CONVERTER OPERATION The core of the LTC2273/LTC2272 are CMOS pipelined multi-step converters with a front-end PGA. As shown in Figure 1, the converter has five pipelined ADC stages. A sampled analog input will result in a digitized value nine clock cycles later (see the Timing Diagram section). The analog input (AIN+, AIN-) is differential for improved common mode noise immunity and to maximize the input range. Additionally, the differential input drive will reduce even order harmonics of the sample and hold circuit. The encode clock input (ENC+, ENC-) is also differential for improved common mode noise immunity. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC, and an error residue amplifier. The function of each stage is to produce a digital representation of its input voltage along with the resulting analog error residue. The ADC of each stage provides the quantization, and the residue is produced by taking the difference between the input voltage and the output of the reconstruction DAC. The residue is amplified by the residue amplifier and passed on to the next stage. The successive stages of the pipeline operate on alternating phases of the clock so that when odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. The pipelined ADC of the LTC2273/LTC2272 has two phases of operation determined by the state of the differential ENC+/ENC- input pins. For brevity, the text will refer to ENC+ greater than ENC- as ENC high and ENC+ less than ENC- as ENC low. When ENC is low, the analog input is sampled differentially onto the input sample-and-hold capacitors, inside the "S/H & PGA" block of Figure 1. On the rising edge of ENC, the voltage on the sample capacitors is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H amplifier during the high phase of ENC. On the falling edge of ENC, the first stage produces its residue which is acquired by the second stage. The process continues to the end of the pipeline. Each ADC stage following the first has additional error correction range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally delayed such that the results can be properly combined in the correction logic before being encoded, serialized, and sent to the output buffer.
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21
LTC2273/LTC2272 APPLICATIONS INFORMATION
SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2273/ LTC2272 CMOS differential sample and hold. The differential analog inputs are sampled directly onto sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when ENC is low, the NMOS transistors connect the analog inputs to the sampling capacitors and they charge to, and track, the differential input voltage. On the rising edge of ENC, the sampled input voltage is held on the sampling capacitors. During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions for high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Common Mode Bias The ADC sample-and-hold circuit requires differential drive to achieve specified performance. Each input should swing 0.5625V for the 2.25V range (PGA = 0) or 0.375V for the 1.5V range (PGA = 1), around a common mode voltage of 1.25V. The VCM output pin (Pin 39) is designed to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with 2.2F or greater.
AIN- CPARASITIC 1.8pF VDD
Input Drive Impedance As with all high performance, high speed ADCs the dynamic performance of the LTC2273/LTC2272 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of ENC the sample-and-hold circuit will connect the 4.9pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally, the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance it is recommended to have a source impedance of 100 or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second.
LTC2273/LTC2272 VDD RPARASITIC 3 CPARASITIC 1.8pF RPARASITIC 3 RON 20 CSAMPLE 4.9pF RON 20
CSAMPLE 4.9pF
AIN+ VDD
1.6V 6k ENC+ ENC- 6k 1.6V
22732 F02
Figure 2. Equivalent Input Circuit
22732f
22
LTC2273/LTC2272 APPLICATIONS INFORMATION
INPUT DRIVE CIRCUITS Input Filtering A first order RC lowpass filter at the input of the ADC can serve two functions: limit the noise from input circuitry and provide isolation from ADC S/H switching. The LTC2273/LTC2272 have very broadband S/H circuits, DC to 700MHz; it can be used in a wide range of applications; therefore, it is not possible to provide a single recommended RC filter. Figures 3, 4a and 4b show three examples of input RC filtering at three ranges of input frequencies. In general, it is desirable to make the capacitors as large as can be tolerated--this will help suppress random noise as well as noise coupled from the digital circuitry. The LTC2273/ LTC2272 do not require any input filter to achieve data sheet specifications; however, no filtering will put more stringent noise requirements on the input drive circuitry. Transformer Coupled Circuits Figure 3 shows the LTC2273/LTC2272 being driven by an RF transformer with a center-tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used; however, as the turns ratio increases so does the impedance seen by the ADC. Source impedance greater than 50 can reduce the input bandwidth and increase
VCM 50 10 T1 8.2pF 35 8.2pF 0.1F 35 10 T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2F 5 AIN- 8.2pF
22732 F03
high frequency distortion. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. Center-tapped transformers provide a convenient means of DC biasing the secondary; however, they often show poor balance at high input frequencies, resulting in large 2nd order harmonics. Figure 4a shows transformer coupling using a transmission line balun transformer. This type of transformer has much better high frequency response and balance than flux coupled center tap transformers. Coupling capacitors are added at the ground and input primary terminals to allow the secondary terminals to be biased at 1.25V. Figure 4b shows the same circuit with components suitable for higher input frequencies.
VCM 2.2F 0.1F ANALOG INPUT 25 0.1F T1 1:1 25 10 10 0.1F 4.7pF 5 AIN+ 4.7pF LTC2273/ LTC2272
5 AIN- 4.7pF
22732 F04a
T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2F
Figure 4a. Using a Transmission Line Balun Transformer. Recommended for Input Frequencies from 100MHz to 250MHz
2.2F 5 AIN+ LTC2273/ LTC2272 0.1F ANALOG INPUT 25 0.1F T1 1:1 0.1F 2.2F 5 2.2pF
VCM
AIN+ LTC2273/ LTC2272
25
5 2.2pF
AIN-
22732 F04b
T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2F
Figure 3. Single-Ended to Differential Conversion Using a Transformer. Recommended for Input Frequencies from 5MHz to 150MHz
Figure 4b. Using a Transmission Line Balun Transformer. Recommended for Input Frequencies from 250MHz to 500MHz
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LTC2273/LTC2272 APPLICATIONS INFORMATION
Direct Coupled Circuits Figure 5 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of any op amp or closed-loop amplifier will degrade the ADC SFDR at high input frequencies. Additionally, wideband op amps or differential amplifiers tend to have high noise. As a result, the SNR will be degraded unless the noise bandwidth is limited prior to the ADC input. Reference Operation Figure 6 shows the LTC2273/LTC2272 reference circuitry consisting of a 2.5V bandgap reference, a programmable gain amplifier and control circuit. The LTC2273/LTC2272 have three modes of reference operation: Internal Reference, 1.25V external reference or 2.5V external reference. To use the internal reference, tie the SENSE pin to VDD. To use an external reference, simply apply either a 1.25V or 2.5V reference voltage to the SENSE input pin. Both 1.25V and 2.5V applied to SENSE will result in a full scale range of 2.25VP-P (PGA = 0). A 1.25V output VCM is provided for a common mode bias for input drive circuitry. An external bypass capacitor is required for the VCM output. This provides a high frequency low impedance path to ground for internal and external circuitry. This is also the
VCM HIGH SPEED DIFFERENTIAL AMPLIFIER ANALOG INPUT 2.2F 25 12pF AIN+ LTC2273/ LTC2272 TIE TO VDD TO USE INTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 1.25V REFERENCE
compensation capacitor for the reference; it will not be stable without this capacitor. The minimum value required for stability is 2.2F . The internal programmable gain amplifier provides the internal reference voltage for the ADC. This amplifier has very stringent settling requirements and is not accessible for external use. The SENSE pin can be driven 5% around the nominal 2.5V or 1.25V external reference inputs. This adjustment range can be used to trim the ADC gain error or other system gain errors. When selecting the internal reference, the SENSE pin should be tied to VDD as close to the converter as possible. If the sense pin is driven externally it should be bypassed to ground as close to the device as possible with 1F (or larger) ceramic capacitor. PGA Pin The PGA pin selects between two gain settings for the ADC front-end. PGA = 0 selects an input range of 2.25VP-P; PGA = 1 selects an input range of 1.5VP-P. The 2.25V input range has the best SNR; however, the distortion will be higher for input frequencies above 100MHz. For applications with high input frequencies, the low input range will have improved distortion; however, the SNR will be 2.4dB worse. See the Typical Performance Characteristics section of this datasheet.
LTC2273/LTC2272 RANGE SELECT AND GAIN CONTROL SENSE 1x OR 2x
INTERNAL ADC REFERENCE
+
CM
+ -
25
-
AIN- 12pF
22732 F05
AMPLIFIER = LTC6600-20, LTC1993, ETC.
2.5V BANDGAP REFERENCE VCM BUFFER 1.25V
Figure 5. DC Coupled Input with Differential Amplifier
2.2F
22732 F06
Figure 6. Reference Circuit
22732f
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LTC2273/LTC2272 APPLICATIONS INFORMATION
LTC2273/LTC2272 VDD TO INTERNAL ADC CLOCK DRIVERS VDD 1.25V VCM 2.2F 2, 3 6 SENSE 2.2F ENC-
22732 F07
1.6V 6k
ENC LTC2273/ LTC2272
+
3.3V 1F
LTC6652-2.5
VDD
1.6V 6k
4, 5, 7 ,8
22732 F08a
Figure 7. A 2.25V Range ADC with an External 2.5V Reference
Figure 8a. Equivalent Encode Input Circuit
0.1F
T1 50
ENC+
100 8.2pF 0.1F 50
LTC2273/ LTC2272
VTHRESHOLD = 1.6V
ENC+ 1.6V ENC- LTC2273/ LTC2272
0.1F
ENC-
22732 F08b
0.1F
22732 F09
T1 = MA/COM ETC1-1-13 RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE
Figure 8b. Transformer Driven Encode
Figure 9. Single-Ended ENC Drive, Not Recommended for Low Jitter
3.3V MC100LVELT22 3.3V 130 Q0 130 ENC+ ENC- 83 83
22732 F10
D0
Q0
LTC2273/ LTC2272
Figure 10. ENC Drive Using a CMOS to PECL Translator
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LTC2273/LTC2272 APPLICATIONS INFORMATION
Driving the Encode Inputs The noise performance of the LTC2273/LTC2272 can depend on the encode signal quality as much as for the analog input. The encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies), take the following into consideration: 1. Differential drive should be used. 2. Use as large an amplitude possible. If using transformer coupling, use a higher turns ratio to increase the amplitude. 3. If the ADC is clocked with a fixed frequency sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs such that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.4V to 3V. Each input may be driven from ground to VDD for single-ended drive. Maximum and Minimum Conversion Rates The maximum conversion rate for the LTC2273 is 80Msps. The maximum conversion rate for the LTC2272 is 65Msps. The lower limit of the LTC2273/LTC2272 sample rate is determined by the PLL minimum operating frequency of 20Msps. For the ADC to operate properly, the internal CLK signal should have a 50% duty cycle. A duty cycle stabilizer circuit has been implemented on chip to facilitate non-50% ENC duty cycles. Data Format The MSBINV pin selects the ADC data format. A low level selects offset binary format (code 0 corresponds to -FS, and code 65535 corresponds to +FS). A high level on MSBINV selects 2's complement format (code -32768 corresponds to -FS and code 32767 corresponds to +FS. Shutdown Modes The assertion of both SHDN pins will shut down the ADC and the serial interface and place the chip in a low-current mode. Internal Dither The LTC2273/LTC2272 are 16-bit ADC with a very linear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. Small errors in the transfer function are usually a result of ADC element mismatches. An optional internal dither mode can be enabled to randomize the input location on the ADC transfer curve, resulting in improved SFDR for low signal levels. As shown in Figure 11, the output of the sample-and-hold amplifier is summed with the output of a dither DAC. The dither DAC is driven by a long sequence pseudo-random number generator; the random number fed to the dither DAC is also subtracted digitally from the ADC result. If the dither DAC is precisely calibrated to the ADC, very little of the dither signal will be seen at the output. The dither signal that does leak through will appear as white noise. The dither DAC is calibrated to result in less than 0.5dB elevation in the noise floor of the ADC, as compared to the noise floor with dither off.
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LTC2273/LTC2272 APPLICATIONS INFORMATION
LTC2273/LTC2272 AIN+ ANALOG INPUT AIN- S/H AMP 16-BIT PIPELINED ADC CORE CMLOUT+ DIGITAL SUMMATION 8b10b ENCODER SERIALIZER CMLOUT-
CLOCK/DUTY CYCLE CONTROL
PRECISION DAC
MULTIBIT DEEP PSEUDO-RANDOM NUMBER GENERATOR
22732 F11
ENC +
ENC -
DITH DITHER ENABLE HIGH = DITHER ON LOW = DITHER OFF
Figure 11. Functional Equivalent Block Diagram of Internal Dither Circuit
SERIALIZED DATA FRAME Prior to serialization, the ADC data is encoded into the 8B/10B format, which is DC balanced, and run-length limited. The receiver is required to lock onto the data and recover the clock with the use of a PLL. The 8B/10B format requires that the ADC data be broken up into 8-bit blocks (octets), which is encoded into 10-bit code groups applying the 8B/10B rules (refer to IEEE Std 802.3-2002 Part 3, for a complete 8B/10B description).
MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
Figure 12 illustrates the generation of one complete 8B/10B frame. The 8 most significant bits of the ADC are assigned to the first half of the frame, and the remaining 8 bits to the second half of the frame. Next, the two resulting octets are optionally scrambled and encoded into their corresponding 8B/10B code. Finally, the two 10-bit code groups are serialized and transmitted beginning with Bit 0 of code group 1.
ADC OUTPUT WORD BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
LSB BIT 0 OCTET ASSIGNMENT
H BIT 7
G BIT 6
F BIT 5
E BIT 4
D BIT 3
C BIT 2
B BIT 1
A BIT 0
H BIT 7
G BIT 6
F BIT 5
E BIT 4
D BIT 3
C BIT 2
B BIT 1
A BIT 0
FIRST OCTET H BIT 7 G BIT 6 F BIT 5 E BIT 4 D BIT 3 C BIT 2 B BIT 1 A BIT 0 H BIT 7 G BIT 6 F BIT 5
SECOND OCTET E BIT 4 D BIT 3 C BIT 2 B BIT 1 A BIT 0
OPTIONAL SCRAMBLER
FIRST SCRAMBLED OCTET a BIT 0 b BIT 1 c BIT 2 d BIT 3 e BIT 4 i BIT 5 f BIT 6 g BIT 7 h BIT 8 j BIT 9 a BIT 0 b BIT 1
SECOND SCRAMBLED OCTET c BIT 2 d BIT 3 e BIT 4 i BIT 5 f BIT 6 g BIT 7 h BIT 8 j BIT 9
8B/10B ENCODER
8B/10B CODE GROUP 1 ONE FRAME BIT 0 OF CODE GROUP 1 IS TRANSMITTED FIRST SERIAL OUT
8B/10B CODE GROUP 2
22732 F12
Figure 12. Evolution of One Transmitted Frame (Compare to IEEE Std 802.3-2002 Part 3, Figure 36-3)
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LTC2273/LTC2272 APPLICATIONS INFORMATION
tAP ANALOG INPUT N tCONV ENC+ N+1 N+2 N+8 N+9 N + 10
tH tL
INTERNAL PARALLEL DATA INTERNAL 8B/10B DATA
N-6
N-5
N-4
N+3
N+4
N-9 tBIT
N-8
N-7 LATP
N
N+1
SERIAL DATA OUT N - 10 N-9 N-8 N-1 N
22732 F13
Figure 13. Timing Relationship of Analog Sample to Serial Data Out
Initial Frame Synchronization In the absence of a frame clock, it is necessary to determine the start of each frame through a synchronization process. To establish frame synchronization, Figures 14 and 15 illustrate the following sequence: * The receiver issues a synchronization request via the synchronization interface. * If the synchronization request is active for more than one ENC clock cycle, the LTC2273/LTC2272 will transmit a synchronization preamble. When the ISMODE pin is low the transmitted preamble will consist of consecutive K28.5 comma symbols in conformance with the JESD204 specification. When the ISMODE pin is high, a series of idle ordered sets will be transmitted. The idle ordered sets consist of a K28.5 comma followed by either D5.6 or D16.2 as defined in IEEE Std 802.3-2002 part3, Clause 36.2.4.12.
* The receiver searches for the expected preamble and waits for the correct reception of an adequate number of preamble characters. * The receiver deactivates the synchronization request. * Upon detecting the deactivation of the synchronization request, the LTC2273/LTC2272 continue to transmit the synchronization preamble until the end of the frame. * At the start of the next frame, the LTC2273/LTC2272 will begin transmitting data characters. * The receiver designates the first data character received after the preamble transmission to be the start of the frame. The first octet of the frame contains the most significant byte of the ADC's output word.
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LTC2273/LTC2272 APPLICATIONS INFORMATION
tCONV N N+1 tHD ENC+ tCS(MIN) SYNC+ tCS(MAX) SERIAL DATA OUT N - 10 N-9 N-8 N-7 K28.5 (x2) K28.5 (x2)
22732 F14a
N+3 N+2 N+4 N+5
ANALOG INPUT
N-1
tSU
LATSC
Figure 14a. SYNC+ Low Transition to Comma Output Timing (ISMODE is Low)
tCONV N N+1 tHD ENC+ tCS(MIN) SYNC+ tCS(MAX) SERIAL DATA OUT K28.5 (x2) K28.5 (x2) K28.5 (x2) N-7 N-6
22732 F14b
N+3 N+2 N+4
ANALOG INPUT
N-1
tSU
LATSD
Figure 14b. SYNC+ High Transition to Data Output Timing (ISMODE is Low)
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LTC2273/LTC2272 APPLICATIONS INFORMATION
START
WAIT FOR NEXT FRAME CLOCK
NO
SYNC REQUEST?
YES
DATA TRANSMISSION FLOW (SEE FIGURE 18)
NO
IS ISMODE ENABLED?
YES
TRANSMIT K28.5 AS CODE GROUP 1
NO
NEGATIVE DISPARITY?
YES
TRANSMIT K28.5 AS CODE GROUP 2 (DISPARITY NOT OK) TRANSMIT K28.5 AS CODE GROUP 1 (NEGATIVE DISPARITY) TRANSMIT D5.6 AS CODE GROUP 2 (NEGATIVE DISPARITY) (DISPARITY IS OK) TRANSMIT K28.5 AS CODE GROUP 1 (POSITIVE DISPARITY) TRANSMIT D16.2 AS CODE GROUP 2 (NEGATIVE DISPARITY)
22732 F15
Figure 15. Initial Synchronization Flow Diagram
Scrambling To avoid spectral interference from the serial data output, an optional data scrambler is added between the ADC data and the 8B/10B encoder to randomize the spectrum of the serial link. The scrambler is enabled by setting the SCRAM pin to a high logic level. The polynomial used for the scrambler is 1 + x14 + x15, which is a pseudo-random pattern repeating itself every 215-1. Figure 16 illustrates the LTC2273/LTC2272 implementation of this polynomial in parallel form.
The scrambled data is converted into two valid 8B/10B code groups, constituting a complete frame. The 8B/10B code groups are then serialized and transmitted. The receiver is required to deserializing the data, decode the code-groups into octets and descramble them back to the original octets using the self-aligning descrambler shown in Figure 17. This descrambler is shown in 16-bit parallel form, which is an efficient implementation of the (1 + x14 + x15) polynomial, operating at the frame clock rate (ADC sample rate).
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LTC2273/LTC2272 APPLICATIONS INFORMATION
SAMPLE_CLK D0 Q D1 Q D2 Q D3 SECOND OCTET D4 Q D5 Q D6 Q D7 Q D8 Q D9 Q D10 Q D11 FIRST OCTET D12 Q D13 Q D13 Q D15 MSB FF D C SF7 MSB FF D C SF6 D FF C SF5 Q D FF C SF4 D FF C SF3 FIRST SCRAMBLED OCTET FF D C SF2 FF D C SF1 FF D C SF0 D FF C SS7 TO 8B/10B ENCODER D FF C SS6 FF D C SS5 Q D FF C SS4 FF D C SS3 SECOND SCRAMBLED OCTET FF D C SS2 D FF C SS1 SS0
FROM ADC
22732 F16
Figure 16. LTC2273/LTC2272 16-Bit 1 + x14 + x15 Parallel Scrambler
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LTC2273/LTC2272 APPLICATIONS INFORMATION
FRAME_CLK LSB D0 D Q FF C D1 SS1 D Q FF C D2 SS2 D Q FF C D3 SECOND SCRAMBLED OCTET SS3 D Q FF C D4 SS4 D Q FF C D5 SS5 D Q FF C D6 SS6 D Q FF C FROM 8B/10B DECODER SS7 D Q FF C D8 SF0 D Q FF C D9 SF1 D Q FF C D10 SF2 D Q FF C D11 FIRST SCRAMBLED OCTET SF3 D Q FF C D12 SF4 D Q FF C D13 SF5 D Q FF C D14 SF6 D Q FF C SF7 MSB D15 MSB
22732 F17
SS0
D7 DESCRAMBLED ADC DATA
Figure 17. Required 16-Bit 1 + x14 + x15 Parallel Descrambler
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LTC2273/LTC2272 APPLICATIONS INFORMATION
Frame Alignment Monitoring After the initial synchronization has been established, it may be desirable to periodically verify that frame alignment is being maintained. The receiver may issue a synchronization request at any time, but data will be lost during the resynchronization interval. To verify frame alignment without the loss of data, frame alignment monitoring is enabled by setting the FAM pin to a high level. In this mode, predetermined data in the second code group of the frame is substituted with the control character K28.7. The receiver is required to detect the K28.7 character and replace it with the original data. In this way, the second code group may be discerned from the first, and the receiver is able to periodically verify the frame alignment without the loss of data (refer to Table 1 and the flow diagram of Figure 18). There are two frame alignment monitoring modes summarized in Table 1. FAM mode 1 is implemented when FAM is high, and SCRAM is low: * When the data in the second code group of the current frame equals the data in the second code group of the
Table 1. Frame Alignment Monitoring Modes
SCRAM PIN FAM Mode 1 Low DDSYNC PIN High ACTION The second code group is replaced with K28.7 if it is equal to the 2nd Code Group of the previous frame The second code group is replaced with K28.7 if it is equal to D28.7 No K28.7 substitutions will take place
previous frame, the LTC2273/LTC2272 will replace the second code group with the control character K28.7 before serialization. However, if a K28.7 symbol was already transmitted in the previous frame, the actual code group will be transmitted. * Upon receiving a K28.7 symbol, the receiver is required to replace it with the data decoded at the same position of the previous frame. FAM mode 2 is implemented when FAM is high and SCRAM is high: * When the data in the second code group of the current frame equals D28.7, the LTC2273/LTC2272 will replace this data with K28.7 before serialization. * Upon receiving a K28.7 symbol, the receiver is required to replace it with D28.7. With FAM enabled the receiver is required to search for the presence of K28.7 symbols in the data stream. If two successive K28.7 symbols are detected at the same position other than the assumed end of frame, the receiver will realign its frame boundary to the new position.
FAM Mode 2 FAM OFF
High X
High Low
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LTC2273/LTC2272 APPLICATIONS INFORMATION
START SCRAMBLE ADC DATA IF SCRAM IS ENABLED
GENERATE 8B/10B CODE-GROUPS 1 AND 2
NO
IS FAM ENABLED?
YES
(FRAME ALIGNMENT MONITORING IS ENABLED)
TRANSMIT CODE GROUP 1 TRANSMIT CODE GROUP 1 NO TRANSMIT CODE GROUP 2 IS CODE GROUP 2 = CODE GROUP 2 OF LAST FRAME? IS SCRAM ENABLED? YES (DATA SCRAMBLING IS ENABLED)
NO
YES
NO
IS CODE GROUP 2 = D28.7?
YES
TRANSMIT CODE GROUP 2 NO WAS K28.7 TRANSMITTED IN LAST FRAME? YES
TRANSMIT CODE GROUP 2
TRANSMIT K28.7 AS CODE GROUP 2
TRANSMIT K28.7 AS CODE GROUP 2
TRANSMIT CODE GROUP 2 END
22732 F18
Figure 18. Data Transmission Flow Diagram
PLL Operation The PLL has been designed to accommodate a wide range of sample rates. The SRR0 and SRR1 pins are used to configure the PLL for the intended sample rate range. Table 2 summarizes the sample clock ranges available to the user.
Table 2. Sample Rate Ranges
SRR1 0 1 1 SRR0 x 0 1 SAMPLE RATE RANGE 20Msps < FS 35Msps 30Msps < FS 65Msps 60Msps < FS 80Msps
Serial Test Patterns To facilitate testing of the serial interface, three test patterns are selectable via pins PAT0 and PAT1. The available test patterns are described in Table 3. A K28.5 comma may be used as a fourth test pattern by requesting synchronization through the SYNC+/SYNC- pins.
Table 3. Test Patterns
PAT1 0 0 1 1 PAT0 0 1 0 1 TEST PATTERNS ADC Data 1010101010 Pattern (8B/10B Code Group D21.5) 1+ x9 + x11 Pseudo Random Pattern 1+ x14 + x15 Pseudo Random Pattern
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LTC2273/LTC2272 APPLICATIONS INFORMATION
High Speed CML Outputs The CML outputs must be terminated for proper operation. The OVDD supply voltage and the termination voltage determine the common mode output level of the CML outputs. For proper operation of the CML driver, the output common mode voltage should be greater than 1V. The directly-coupled termination mode of Figure 19a is recommended when the receiver termination voltage is within the range of 1.2V to 3.3V. When the CML outputs are directly-coupled to the 50 termination resistors, the OVDD supply voltage serves as the receiver termination voltage, and the output common mode voltage will be approximately 200mV lower than OVDD. The directly-coupled differential termination of Figure 19b may be used in the absence of a receiver termination voltage within the required range. In this case, the common mode voltage is shifted down to approximately 400mV below OVDD, requiring an OVDD in the range of 1.4V to 3.3V. If the serial receiver's common mode input requirements are not compatible with the directly-coupled termination modes, the DC balanced 8B/10B encoded data will permit the addition of DC blocking capacitors as shown in Figure 19c. In this AC-coupled mode, the termination voltage is determined by the receiver's requirements. The coupling capacitors should be selected appropriately for the intended operating bit-rate, usually between 1nF to 10nF In the AC. coupled mode, the output common mode voltage will be approximately 400mV below OVDD, so the OVDD supply voltage should be in the range of 1.4V to 3.3V. Grounding and Bypassing The LTC2273/LTC2272 require a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the LTC2273/LTC2272 have been optimized for a flowthrough layout so that the interaction between inputs and digital outputs is minimized. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, VCM, and OVDD pins. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC2273/LTC2272 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Heat Transfer Most of the heat generated by the LTC2273/LTC2272 are transferred from the die through the bottom-side exposed pad. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board. It is critical that the exposed pad and all ground pins are connected to a ground plane of sufficient area with as many vias as possible.
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LTC2273/LTC2272 APPLICATIONS INFORMATION
SERIAL CML DRIVER 1.2V TO 3.3V OVDD 50 50 CMLOUT+ 50 TRANSMISSION LINE 50 50 SERIAL CML RECEIVER
CMLOUT- DATA+ DATA- 16mA 50 TRANSMISSION LINE
GND
22732 F19a
Figure 19a. CML Termination, Directly-Coupled Mode (Preferred)
SERIAL CML DRIVER OVDD 50 50 CMLOUT+ 1.4V TO 3.3V 50 TRANSMISSION LINE
SERIAL CML RECEIVER
CMLOUT- DATA+ DATA- 16mA 50 TRANSMISSION LINE
100
GND
22732 F19b
Figure 19b. CML Termination, Directly-Coupled Differential Mode
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LTC2273/LTC2272 APPLICATIONS INFORMATION
SERIAL CML DRIVER 1.4V TO 3.3V OVDD 50 50 CMLOUT+ 50 TRANSMISSION LINE 50 50 VTERM SERIAL CML RECEIVER
0.01F
CMLOUT- DATA+ DATA- 16mA
0.01F
50 TRANSMISSION LINE
GND
22732 F19c
Figure 19c. CML Termination, AC-Coupled Mode
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LTC2273/LTC2272 TYPICAL APPLICATIONS
Silkscreen Top
Top Side
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38
LTC2273/LTC2272 TYPICAL APPLICATIONS
Inner Layer 2
Inner Layer 3
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LTC2273/LTC2272 TYPICAL APPLICATIONS
Inner Layer 4
Inner Layer 5
22732f
40
LTC2273/LTC2272 TYPICAL APPLICATIONS
Bottom Side
Silkscreen Bottom
22732f
41
RX_ER
PLL1
PLL0
ISMODE
DITH
PAT0
PAT1
PGA
MSBINV
PDADC
PDSER
FAM
3.3V 4 3 5 7 9 11 13 15 17 19 21 23 25 28 30 32 R27D 33 2.5V 2.5V C37 0.01F R45 10k R47 OPTIONAL 30 29 28 27 26 25 24 23 22 TX_ER LOOPEN TX_EN 21 20 PBUS5 PBUS4 TXD14 GND TXD15 C24 0.01F R46 10k R28 825 R29 825 34 36 38 40 42 44 46 48 50 52 54 D1 SYNC ERR D2 DATA GOOD PBUS7 PBUS6 56 58 60 62 64 66 16 17 18 19 1 2 15 3 PBUS3 PBUS2 68 70 72 PBUS1 PBUS0 74 76 78 PBUS15 80 PBUS14 82 RX_ER 84 PBUS13 PBUS12 86 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 27 29 31 33 35 37 39 41 43 45 47 49 51 53 6 INT SDA PFC8574TS A2 A1 NC NC NC NC VSS 3.3V A0 20 22 24 3 8 13 18 15 6 18 7 3.3V 16 9 14 SCL SCL 2 12 4 SDA 10 1 8 5 P7 P6 P5 P4 P3 P2 P1 VDD P0 INT SDA 4 SDA SCL 2 9 7 6 1 VDD 20 19 17 16 14 12 11 10 5
SCRAM
P7
P6
P5
P4
P3
P2
P1
8 PLL0 ISMODE DITH 9 10 12 NC NC NC NC VSS 14 3 8 13 18 15 PGA A0 PAT1 A1 SYNC R54 OPTIONAL MSBINV HEADER OPTIONAL 13 11 PAT0 A2 7 8 SCRAM PFC8574TS SCL 5 6 FAM 3 4 PDSER
R11 10k
SHDN
SENSE
5
C33 10F 0805 P0 PLL1 1 2 PDADC
GND
7
EX_3.3V PBUS0 PBUS1 PBUS2 PBUS3 PBUS4 PBUS5 PBUS6 PBUS7 PBUS8 PBUS9 PBUS10 PBUS11 PBUS12 PBUS13 PBUS14 PBUS15 26
GP
LTC2273/LTC2272
TYPICAL APPLICATIONS
GND
GP
VDD
GND
VDD
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
RXD8
RXD10
RXD11
RXD12
RXD13
RXD14
C13 0.1F R13 49.9k 52 GNDA DINRXN DINRXP VDDA RREF VDDA GNDA DOUTTXN DOUTTXP GNDA VDD ENABLE *U3 LCKREFN PRBSEN TESTEN GND RX_ER/PRBS_PASS RX_DV/LOS C26A 1nF 53 54 55 C27A 1nF 57 58 59 60 61 PDSER PDADC PLL1 PLL0 ISMODE DITH TXD0 TXD1 TXD2 VDD TXD3 TXD4 TXD5 GND TXD6 TXD7 VDD TXD8 TXD9 TXD10 GND TXD11 TXD12 PAT0 PAT1 MSBINV SCRAM FAM R44 1k C23 0.01F C25 0.01F SYNC OPTIONAL 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 L2 FERRITE BEAD BLM1866470SN1D TXD13 GTX_CLK C32 0.01F C21 0.01F C22 0.01F 56 CMLOUT+ CMLOUT- SYNC- SYNC+ 28 20 19 18 17 16 15 32 33 36 34 31 29 23 24 C26B 1nF 22 25 OVDD OVDD R12 49.9k
C15 0.01F
VDD
VDD
VDD
L1* AIN
+
T3* 4
T1 MABAES0060 R1 10
5 R15 OPTIONAL 5 R2 10 PDADC 35 PGA VCM SENSE DITH PAT0 9 ENC MSBINV SCRAM FAMON GND GND GND GND GND GND GND GND OGND OGND OGND OGND GND ENC-
+
C5 0.1F AIN- PDSER
1 2
5
1 2
R3 68.1
J2 SIG IN
R18 1000
C1*
4*
*3
4*
*3
R4 68.1
R19* PGA VCM 39 PLL0 ISMODE 38 U1 LTC2272CUJ/LTC2273CUJ PLL1
R5*
C4 0.1F
R51 68.1
R52 68.1
C3*
C2*
R17 10
C20 0.01F
C6 0.1F
R6 100
C16 202F
VDD
R16 10
1
2
12
13
C10 0.1F 10 R11 100
J5 ENCODE
6
SUM
PORT1
3
T2 MABA-007159-000000
R9 4.99 PAT1
RX_CLK
RXD15
7
13
RXD9
GND
*
*
GND
GND
DITH
ISMODE
PLL0
PLL1
PDADC
PDSER
FAM
SCRAM
PAT0
PAT1
PGA
MSBINV
VCC
*VERSION TABLE
8 VCC SCL SDA 24LC32A-I/ST WP A2 A1 VSS A0 4 6 5 7 3 2 1 SCL SDA WP 24LC025-I/ST
8 VCC SCL SDA WP A2 A1 VSS A0 4 6 5 7 3 2 1
SW1 MAIN SYNC EVQPPDA25
R37 4750 R38 4750
GND
42
2 1 3.3V INT_SYNC R53 1k 20 19 17 16 14 12 11 10 OVDD C18 10F 0805 L4 FERRITE BEAD BLM1866470SN1D 3.3V 2.5V R20 200 R21 825 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 C36 0.01F C26 0.1F C12 3.3V 0.1F OVDD C14 0.01F C27B 1nF J7 CMLOUT+ J6 CMLOUT- R23B 33 R23C 33 R24A 33 R24B 33 R25A 33 R25B 33 R26A 33 R26B 33 R27C 33 R23D 33 R24C 33 R24D 33 R25C 33 R25D 33 R26C 33 R26D 33 JP2 RUN SHDN 3 41 NC7SZ332PSX INT_SYNC C VCC Y B 3 PBUS11 S2 S3 S4 PBUS10 3.3V 5 PBUS8 R32 10 2 4 C25 0.01F NC7SP17P5X SCL SDA WP GND 2 A 3.3V OFF 4 2 3 4 1 R14 33.2 2 3 4 1 2 3 4 1 OFF OFF 5 6 R43 10k 1 6 7 8 11 14 37 40 21 26 27 30 C8 8.2pF 8 7 6 5 8 7 6 5 8 7 6 5 88 90 92 94 96 NC7SVU04P5X 3 GND VCC C28 0.01F PBUS9 98 100 87 89 91 93 95 97 99 1 7 5 3 1A OE1 2A OE2 R50 OPTIONAL 2B 4 6 SDA NC7WB66K8X R39 1000 3.3V 8 1B 2 SCL R48 OPTIONAL R49 OPTIONAL 2.5V 3.3V 4 L1 56nH 18nH 56nH 18nH 56nH 18nH R5, R19 86.6 43.2 86.6 43.2 86.6 43.2 T3 MABA-007159 WBC1-1LB MABA-007159 WBC1-1LB MABA-007159 WBC1-1LB INPUT FREQUENCY 1MHz TO 70MHz 70MHz TO 140MHz 1MHz TO 70MHz 70MHz TO 140MHz 1MHz TO 70MHz 70MHz TO 140MHz R40 4750 C35 0.01F
22732 TA02
LT1763CDE-2.5
10
11
IN
OUT
2
IN
OUT
3
2.5V
1
4
NC
9
NC
C34 0.01F
12
NC
BYP
6
NC
13
TP1 EX_3.3V
L3 FERRITE BEAD BLM1866470SN1D
3.3V
ADC 3.3V
TP2 GND
C17 4.7F 0805
LT1763CDE
OVDD
10
11
IN
OUT
2
IN
OUT
3
R36 10k
8
SHDN
SENSE
5
1
R22 1000
4
NC
9
NC
C19 0.01F
12
NC
BYP
6
R31 4.32k
NC
4
SBTC-2-10L+
5
NC
PORT2
4
R34 34
3 2
R7 4.99
5
1
R8 4.99
82pF
1
2
C9 0.1F
3.3V
VDD
3
C11 0.1F
R10 4.99
SENSE
2
TP3 EXT REF
GND
1
TP4 GND
2.5V
C30 0.1F
J8 CLKOUT
R32 10k
2
R55 OPTIONAL
R56 0
R35 49.9
R33 10k
ASSEMBLY TYPE DC1151A-C DC1151A-D DC1151A-E DC1151A-F DC1151A-G DC1151A-H
U1 LTC2274CU LTC2274CU LTC2273CU LTC2273CU LTC2272CU LTC2272CU
U3 TLK2501 TLK2501 TLK2501 TLK2501 TLK1501 TLK1501
CML DATA RATE 1.5GHz TO 2.5GHz 1.5GHz TO 2.5GHz 1.5GHz TO 2.5GHz 1.5GHz TO 2.5GHz 0.6GHz TO 1.5GHz 0.6GHz TO 1.5GHz
ADC SAMPLE RATE 105Msps 105Msps 80Msps 80Msps 65Msps 65Msps
C1 4.7pF 1.8pF 4.7pF 1.8pF 4.7pF 1.8pF
C2, C3 8.2pF 3.9pF 8.2pF 3.9pF 8.2pF 3.9pF
22732f
LTC2273/LTC2272 PACKAGE DESCRIPTION
UJ Package 40-Lead Plastic QFN (6mm x 6mm)
(Reference LTC DWG # 05-08-1728 Rev O)
0.70 0.05
6.50 0.05 5.10 0.05 4.42 0.05 4.50 0.05 (4 SIDES)
4.42 0.05
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
6.00 0.10 (4 SIDES)
0.75
0.05 R = 0.10 TYP
R = 0.115 TYP
39 40 0.40 1 PIN 1 NOTCH R = 0.45 OR 0.35 45 CHAMFER 2 0.10
PIN 1 TOP MARK (SEE NOTE 6)
4.50 REF (4-SIDES)
4.42 0.10
4.42 0.10
(UJ40) QFN REV O 0406
0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 BOTTOM VIEW--EXPOSED PAD
0.05
0.50 BSC
22732f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
43
LTC2273/LTC2272 RELATED PARTS
PART NUMBER LTC1993-2 LTC1994 LTC2215 LTC2216 LTC2217 LTC2202 LTC2203 LTC2204 LTC2205 LTC2206 LTC2207 LTC2208 LTC2209 LTC2220 LTC2220-1 LTC2224 LTC2249 LTC2250 LTC2251 LTC2252 LTC2253 LTC2254 LTC2255 LTC2274 LTC2284 LTC2299 LTC5512 LTC5515 LTC5516 LTC5517 LTC5522 LTC5527 LTC5579 LTC6400-20 DESCRIPTION High Speed Differential Op Amp Low Noise, Low Distortion Fully Differential Input/ Output Amplifier/Driver 16-Bit, 65Msps, Low Noise ADC 16-Bit, 80Msps, Low Noise ADC 16-Bit, 105Msps, Low Noise ADC 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 16-Bit, 25Msps, 3.3V ADC, Lowest Noise 16-Bit, 40Msps, 3.3V ADC 16-Bit, 65Msps, 3.3V ADC 16-Bit, 80Msps, 3.3V ADC 16-Bit, 105Msps, 3.3V ADC 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 16-Bit, 160Msps, ADC, LVDS Outputs 12-Bit, 170Msps ADC 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 14-Bit, 80Msps ADC 10-Bit, 105Msps ADC 10-Bit, 125Msps ADC 12-Bit, 105Msps ADC 12-Bit, 125Msps ADC 14-Bit, 105Msps ADC 14-Bit, 125Msps, 3V ADC, Lowest Power 16-Bit, 105Msps, Serial ADC 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk Dual 14-Bit, 80Msps ADC DC-3GHz High Signal Level Downconverting Mixer 1.5 GHz to 2.5GHz Direct Conversion Quadrature Demodulator 800MHz to 1.5GHz Direct Conversion Quadrature Demodulator 40MHz to 900MHz Direct Conversion Quadrature Demodulator 600MHz to 2.7GHz High Linearity Downconverting Mixer 400MHz to 3.7GHz High Signal Level Downconverting Mixer 1.5GHz to 3.8GHz High Linearity Upconverting Mixer 1.8GHz Low Noise, Low Distortion Differential ADC Driver for 300MHz IF COMMENTS 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain Low Distortion: -94dBc at 1MHz 700mW, 81.5dB SNR, 100dB SFDR, 64-Pin QFN 970mW, 81.3dB SNR, 100dB SFDR, 64-Pin QFN 1190mW, 81.2dB SNR, 100dB SFDR, 64-Pin QFN 140mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN 220mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN 480mW, 79dB SNR, 100dB SFDR, 48-Pin QFN 590mW, 79dB SNR, 100dB SFDR, 48-Pin QFN 725mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN 900mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN 1250mW, 77.7dB SNR, 100dB SFDR, 64-Pin QFN 1.45W, 77.1dB SNR, 100dB SFDR, 64-Pin QFN 890mW, 67.5dB SNR, 9mm x 9mm QFN Package 910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN 230mW, 73dB SNR, 5mm x 5mm QFN Package 320mW, 61.6dB SNR, 5mm x 5mm QFN Package 395mW, 61.6dB SNR, 5mm x 5mm QFN Package 320mW, 70.2dB SNR, 5mm x 5mm QFN Package 395mW, 70.2dB SNR, 5mm x 5mm QFN Package 320mW, 72.5dB SNR, 5mm x 5mm QFN Package 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN 1.3W, 100dB SFDR, High Speed Serial Interface (JESD204), 6mm x 6mm QFN Package 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN 230mW, 71.6dB SNR, 5mm x 5mm QFN Package DC to 3GHz, 21dBm IIP3, Integrated LO Buffer High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50 Single-Ended RF and LO Ports 4.5V to 5.25V Supply, 23.5dBm IIP3 at 1900MHz, ICC = 78mA, Conversion Gain = 2dB 3.3V Supply, 27.3dBm OIP3 at 2.14GHz, Conversion Gain = 2.6dB at 2.14GHz Fixed Gain 10V/V, 2.1nVHz Total Input Noise, 3mm x 3mm QFN-16 Package
22732f
44 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 1208 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2008

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